On August 18, 2026, Velaura announced a $110M Series A at a post-money valuation of more than $1 billion. The round was led by Seligman Ventures, with participation from Capricorn Investment Group and existing investors including Mayfield, Maverick Silicon, MARA, Premji Invest, Samsung Catalyst Fund, and StepStone Group.

Before the rebrand from Auradine to Velaura in March 2026, the company had raised over $300M across several rounds.

The Series C, raised in April 2025 at $153M total (comprising $138M in equity and $15M in venture debt), was led by StepStone Group, with participation from Maverick Silicon, Premji Invest, Samsung Catalyst Fund, MARA Holdings, GSBackers, Top Tier Capital Partners, MVP Ventures, and Cota Capital. The original Series A of $81M, raised in May 2023, was led by Celesta Capital and Mayfield, with DCVC and Stanford University also participating.

Velaura builds ultra-low-power compute infrastructure for AI workloads across two product tracks: a silicon design and IP platform for cloud AI accelerators, and an emerging hardware-plus-software platform for physical AI systems such as robots, drones, and autonomous machines.

Its cloud AI product, Titan Core, is a design toolkit and IP layer rather than a finished chip. A hyperscaler or XPU vendor brings existing RTL, the blueprint for its AI accelerator, and Velaura applies proprietary low-voltage digital design libraries, custom EDA flows, and physical implementation methods to return either an optimized GDS layout or a chiplet. The customer's software stack, models, and architecture remain intact; Velaura changes the implementation layer underneath so the finished silicon runs at lower voltage and consumes less power. The company says this approach can cut overall AI accelerator power by up to 2x, with the largest gains in matrix-multiplication arithmetic blocks, which account for roughly 40–70% of XPU power consumption.

For hyperscalers, the pitch is shorter development time and lower execution risk. Building low-voltage silicon expertise internally at advanced nodes like 3nm and 2nm takes years and introduces yield and reliability risk. Velaura says its engagement model fits into an existing roadmap and can compress that timeline by two to three years.

The Physical AI platform is a separate, still-emerging product for robotics and autonomy developers rather than silicon teams. The stack includes a purpose-built SoC, a compiler that ingests models from PyTorch, ONNX, and TensorFlow Lite, a runtime for scheduling and memory management, and middleware connecting to ROS2 and DDS for robotics integration. The operating constraint is battery and thermal budget: for robots and autonomous machines, compute efficiency determines whether a system can run in the field for hours rather than remain a lab demo.

Velaura also operates its Teraflux blockchain hardware line, which includes air-, immersion-, and hydro-cooled bitcoin mining ASICs, along with FluxOS firmware and FluxVision fleet management software. Beyond its role as a revenue source, Teraflux serves as a proof point for the company's low-voltage silicon approach: Velaura cites over 30 million ASICs shipped in production as evidence that its design methods work at scale.

Velaura spans two B2B architectures at different points on the hardware-to-IP spectrum.

The Teraflux mining hardware business follows a traditional product-and-fleet-sales model. Bitcoin data center operators purchase ASIC mining systems and pay for ongoing firmware, fleet management software, and energy optimization features. Revenue is hardware-driven, margins are constrained by bill-of-materials and manufacturing costs, and go-to-market relies on high-touch sales to large anchor customers.

The AI compute business uses a different model. Titan Core monetizes through a mix of engineering engagement fees and licensable IP. A customer brings its RTL and design priorities; Velaura charges for specialized design work and embeds its proprietary low-voltage libraries and EDA flows into the output. This structure captures revenue earlier in the design cycle than a pure royalty model and can create longer-lived IP relationships within customer programs across chip generations.

The Physical AI platform, still under development, suggests a third model: hardware paired with enabling software, where the SoC or chiplet is the primary revenue vehicle and the compiler, runtime, and robotics middleware stack drives adoption and retention without necessarily being the largest direct revenue line.

Across the three models, the economic pitch is efficiency. A 250–500W reduction on a 1,000W XPU translates into lower cooling costs, higher rack density, and deferred facility expansion for a hyperscaler; for a robotics team, it translates into longer battery life and smaller thermal envelopes. This barbell structure, with higher-potential-margin AI IP on one side and operationally intensive hardware on the other, means the overall margin profile will depend heavily on how quickly revenue mix shifts toward the AI platform.

Velaura competes in two arenas: as a power-efficiency layer inside cloud AI silicon programs, and as a compute platform for physical AI systems. The competitive dynamics differ across those markets.

NVIDIA is the default reference point for many robot and autonomous-system developers. Jetson and IGX Thor provide a cloud-to-edge stack tied to CUDA, JetPack, Isaac, and GR00T-related robotics tooling, so NVIDIA competes on chip efficiency, developer lock-in, and procurement simplicity.

Qualcomm uses a similar playbook through Dragonwing, combining on-device AI, connectivity, and embedded OEM relationships into a baseline many production robotics programs adopt. NXP, after closing its acquisition of Kinara in October 2025, adds automotive and industrial qualification pathways to a pre-integrated edge AI platform, the kind of vertical bundling that can pressure a design-layer player like Velaura.

Companies like Figure run onboard low-power compute for robot control rather than depending on the cloud, and BrightAI uses edge AI chips for battery-powered monitoring in physical infrastructure. Those examples point to the demand Velaura is targeting, while also underscoring competition from platform vendors that already hold those design wins.

Hailo, Axelera, SiMa.ai, and Ambarella sell more complete solutions than Velaura currently does, typically bundling silicon with SDKs, dev kits, and reference designs that let OEMs make a procurement decision without custom silicon work.

SiMa.ai overlaps most directly with Velaura's physical AI positioning, with its Modalix platform targeting industrial PCs, edge servers, and robotics under a turnkey deployment model. Hailo's 10H is positioned around always-on edge inference at roughly 2.5W, and Axelera claims 15 TOPS/W on its Metis platform with developer-ready boards. Both address the same buyer pain point Velaura targets.

Velaura's counter-position is that it can improve a customer's own silicon rather than asking that customer to adopt a third-party architecture. That is a stronger wedge with sophisticated OEMs that want product differentiation, and a harder sell to buyers that prefer deployable modules over IP engagements.

Broadcom and Marvell represent a different form of competitive pressure. Both have become key partners for custom AI accelerators and advanced packaging at the hyperscaler level, Broadcom through programs like the OpenAI Jalapeño intelligence processor, Marvell through its growing custom XPU business. If those players increasingly bundle power optimization into broader custom infrastructure contracts, the space for an independent low-voltage layer like Velaura narrows.

Synopsys is a subtler but material threat. If mainstream EDA vendors productize more low-voltage foundation IP and near-threshold design flows, Velaura's differentiation could be perceived as a services-heavy add-on rather than a distinct category. Efficient Computer and Mythic are the closest architectural analogs among startups, both targeting the same power-efficiency narrative, though with more radical architectural bets than Velaura's compatibility-first approach.

Velaura's expansion logic runs in two directions: moving up the value chain from IP into fuller platform products, and moving across markets from cloud AI into physical AI. Both vectors are already in motion.

The clearest near-term expansion path is from low-power silicon IP into a broader compute platform. Today Titan Core is an IP and design-services offering, but the hiring footprint for compiler leads, runtime architects, and platform software engineers points to a move toward a deployable accelerator platform, where value capture is higher and customer switching costs are stronger.

The chiplet ecosystem creates a specific structural opportunity. Velaura already lists custom ultra-low-power chiplet solutions as an output, and TSMC's 2nm entering high-volume manufacturing in late 2025, alongside N2P and A16 volume production scheduled for the second half of 2026, is pushing more customers toward multi-die designs. Velaura can participate in that shift by becoming a specialist provider of ultra-low-power compute tiles inside broader accelerator packages, attaching to the custom silicon wave rather than being displaced by it.

Physical AI is the largest medium-term TAM expansion. Velaura's purpose-built Physical AI SoC roadmap, combined with its compiler, runtime, and ROS2 integration work, suggests it is building the components needed to sell into production robotics programs rather than just lab demos.

The demand signal is visible in end-market forecasts and buyer profiles. Industrial robot installations are forecast to grow from 541,000 in 2024 to over 600,000 by 2027, and the humanoid and AMR segments are earlier and faster-moving. Companies like Anvil, Foundation, Physical Intelligence, Skild AI, and Galbot represent the type of physical AI builders that need onboard compute with strict power and thermal budgets, the use case Velaura's platform is being built to serve.

Because robots and drones cannot depend on constant cloud connectivity, the value of local inference is structural rather than optional. That makes power efficiency a first-order design variable rather than a secondary feature, which improves Velaura's fit relative to general-purpose edge platforms.

The IEA projects global data-center electricity consumption reaching roughly 945 TWh by 2030, with accelerated servers growing around 30% annually. That makes power efficiency a board-level issue for hyperscalers, not just an engineering preference, expanding Velaura's addressable market beyond specialist chip design shops into organizations facing hard power constraints.

The same dynamic applies across regions. Power-constrained AI deployment is global, and any region where grid constraints, permitting friction, or cooling costs make incremental AI capacity expensive becomes a plausible market for Velaura's efficiency argument. The U.S. hyperscale market is the immediate opportunity, but the same logic applies to European and Asian data center buildouts as AI infrastructure investment accelerates worldwide.

Customer concentration: Velaura's 2025 revenue base appears concentrated in a small number of bitcoin mining hardware customers, with MARA Holdings alone accounting for over $110M in product purchases through September 2025, so any reduction in that relationship or in bitcoin mining capex more broadly would create a material revenue gap before the AI compute business reaches comparable scale.

Platform incompleteness: Competitors like NVIDIA, Qualcomm, NXP, Hailo, and SiMa.ai can sell a board, module, SoC, SDK, or full reference design today, while Velaura currently sells an enabling layer that requires sophisticated customers with their own silicon roadmaps, making it strategically relevant but commercially less visible in the larger market of OEMs and robotics vendors that prefer deployable subsystems over design services and IP.

Scope overextension: Velaura is simultaneously building AI silicon IP for hyperscalers, a full Physical AI SoC with compiler and runtime stack, and continuing to operate a blockchain hardware business, a breadth of parallel execution that raises the risk of being stretched across too many layers before establishing a durable wedge in any one of them.